1. Field of the Invention
The invention relates generally to electronic digital logic circuits, and more specifically to latch circuits having input gating networks which are constructed in accordance with emitter coupled logic design techniques.
2. Description of the Prior Art
Emitter coupled logic circuits, which, with current mode logic circuits, form a type of switch circuit generally referred to as current steering logic, were first developed a number of years ago to provide extremely fast switching times in digital applications. In an emitter coupled logic circuit, a pair of high-gain transistors are used in which the emitters are connected together to form a node to which a constant current source is also connected. The current source limits the total amount of current which is permitted to flow through both transistors at any one time. The base of one of the transistors, termed here a "reference transistor", is connected to a reference voltage and the base of the other transistor, termed here an "input transistor", is connected to the input signal. When the potential, or voltage, level of the input signal is significantly below that of the reference, the reference transistor is turned on so as to conduct current and, if the input signal is low enough, the input transistor is off. When the voltage level of the input signal increases to a point near that of the reference, the input transistor also begins to turn on. With the level of the input signal rising, the input transistor responds by conducting an increasing amount of current thereby increasing the potential level of the node controlled by the current source. Since the potential level of the node is increasing, the potential difference between the base and the emitter of the reference transistor decreases and the reference transistor begins to turn off. Eventually, the level of the input signal increases to a point at which the heavy current through the input transistor causes current starvation through the reference transistor. When the input signal again falls, the reverse operation occurs. The circuit comprising the two transistors and the constant current source essentially forms a two-state switch, with the states of the switch being reflected in the two transistors being alternately on and off, with the input signal operating to steer current between the two transistors.
Emitter coupled logic circuits have been used for a number of years in digital applications which required relatively fast switching speeds. In current emitter coupled logic circuits, neither the input transistor nor the reference transistor is turned completely off or driven into saturation. Instead, the states of the switch are reflected in the relative current levels of the transistors. Since neither transistor is driven into saturation, the states of a logic transistor pair can be switched very rapidly, especially if the current levels reflecting the states are close together. Furthermore, since the two transistors have complementary states, it is possible to obtain complementary output signals with no additional circuitry.
In many applications, it is desirable to provide a latch circuit which has multiple stages of Boolean logic functions as the input. The latch circuit transmits the Boolean result of the input logic network as an output signal as long as a clock signal is in a selected condition indicating that the Boolean result should be passed. When the clock signal shifts to a complementary condition and while it remains in that condition, the latch circuit is in a hold condition in which it holds the state of the prior passed signal, and continues to transmit it as the output signal.
A performance problem with such prior latch circuits is that they typically had two emitter coupled logic switch circuits in time sequence, between the input terminals and the output terminals. The composite Boolean input gating logic portion of the circuit was formed within one emitter coupled logic switch, and the latch was connected from the output of the gating logic, was also formed from a seperate emitter coupled logic switch. This circuit arrangement requires two current switching times, one for each of the sequentially connected emitter coupled logic switches, to allow the resulting signal to be propagated from the Boolean input terminals of the circuit to the latch output terminals.